Researchers have built and demonstrated a novel configurable computing device that uses a thousand times less electrical power – and can be built up to a hundred times smaller – than comparable digital floating-gate configurable devices currently in use.
The new device, called the Field-Programmable Analog Array (FPAA) System-On-Chip (SoC), uses analog technology supported by digital components to achieve unprecedented power and size reductions. The researchers said that for many applications these low-power analog-based chips are likely to work as well as or better than configurable digital arrays.
This paper presents an analog-digital hardware-software co-design environment for simulating and programming reconfigurable systems. The tool simulates, designs, as well as enables experimental measurements after compiling to configurable systems in the same integrated design tool framework. High level software in Scilab/Xcos (open-source programs similar to MATLAB/Simulink) that converts the high-level block description by the user to blif format (sci2blif), which acts as an input to the modified VPR tool, including the code v p r 2 s w c s , encoding the specific platform through specific architecture files, resulting in a targetable switch list on the resulting configurable analog–digital system. The resulting tool uses an analog and mixed-signal library of components, enabling users and future researchers access to the basic analog operations/computations that are possible.
Ref: A Programmable and Configurable Mixed-Mode FPAA SoC. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (7 January 2016) | DOI: 10.1109/TVLSI.2015.2504119
This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (μP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 μW to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600,000x higher density than other non-FG approaches.
Ref: Integrated Floating-Gate Programming Environment for System-Level ICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (29 December 2015) | DOI: 10.1109/TVLSI.2015.2504118
We present the first integrated system to handle heterogeneously used and programmed floating-gate (FG) elements in a single modular approach. We focus on IC design, integration, characterization, and algorithmic development of an integrated FG programming system for a large-scale field-programmable analog array. We work through tunneling approaches to initialize the FG devices for precision programming, as well as hot-electron injection approaches for precise device programming.