A new highly efficient power amplifier for electronics could help make possible next-generation cell phones, low-cost collision-avoidance radar for cars and lightweight microsatellites for communications.
Fifth-generation, or 5G, mobile devices expected around 2019 will require improved power amplifiers operating at very high frequencies. The new phones will be designed to download and transmit data and videos faster than today's phones, provide better coverage, consume less power and meet the needs of an emerging "Internet of things" in which everyday objects have network connectivity, allowing them to send and receive data.
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Ref: A Highly Efficient mm-Wave CMOS SOI Power Amplifier. Sultan R. Helmi, and Saeed Mohammadi Purdue University, West Lafayette, IN, 47907, USA
Three mm-wave power amplifiers (PAs), each with 6 stacked transistors, are implemented in GlobalFoundries 45 nm CMOS SOI technology. As experimentally demonstrated, the design with two triple-Cascode cells with combined transistor layouts achieves the best power performance among the three designs. It achieves a power-added efficiency (PAE) of higher than 40% at 46 GHz and a relatively good power performance from 42 to 54 GHz. At 46 GHz the PA, biased under 6 V, measures a saturated output power (PSAT) of 22.4 dBm, a linear gain of 17.4 dB, a peak PAE of 42%, and a drain efficiency (DE) of 49%. Under a smaller supply voltage of 4.8 V, PSAT is reduced to 20 dBm while DE and peak PAE increase to 53% and 45%, respectively.
Ref: High-Efficiency Microwave and MM-Wave Stacked Cell CMOS SOI Power Amplifiers. Sultan R. Helmi, Student Member, IEEE, Jing-Hwa Chen, Student Member, IEEE, and Saeed Mohammadi, Senior Member, IEEE
Design and implementation of high efficiency microwave and mm-wave CMOS SOI power amplifiers (PAs) based on stacked cell approach is presented. A triple Cascode cell (CS-CG-CG, CS: Common-Source, CG: Common-Gate) as building block of the stacked cell PA facilitates high gain, high power, high efficiency and compact design. Two stacked cell PAs have been implemented in a standard 45 nm CMOS Silicon on Insulator (SOI) technology. The first PA operating at K-Band (24 to 28 GHz) is designed with three stacked triple Cascode cells. Each cell uses three standard transistors with separate layout. At 24 GHz, the K-Band PA biased under a supply voltage of 10.8 V measures a maximum linear power gain of 13 dB, a saturated output power PSAT of 25.3 dBm, a -1 dB output power P1dB of 23.8 dBm and a peak power-added efficiency PAE of 20%. The second PA targeted at U-Band frequencies is designed with two stacked triple Cascode cells. Transistors (CS-CG-CG) in this design have a combined layout to mitigate internodal parasitic capacitances, leading to significant improvement in the PAE at mm-wave frequencies. The U-Band PA achieves a relatively good power performance from 42 to 54 GHz. At 46 GHz, the PA, biased under a supply voltage of 6 V, measures a saturated output power (PSAT) of 22.4 dBm, a linear gain of 17.4 dB, and an unprecedented peak PAE of 42%.